The present disclosure relates to semiconductor devices and methods for fabricating semiconductor devices, and more particularly to a semiconductor device including a through-hole electrode penetrating a semiconductor substrate and a method for fabricating such a semiconductor device.
Stacked-type semiconductor devices including stacks of semiconductor chips for enhanced function and increased degrees of integration have been developed in recent years. In many conventional stacked-type semiconductor devices, semiconductor chips are stacked with intermediate substrates such as interposers sandwiched therebetween, and are electrically connected to each other by wire bonding. Consequently, the wire length increases to cause an increase in wire resistance, resulting in limitation of high-speed operation of the semiconductor devices. In addition, extension of wires increases the entire size of the semiconductor devices, resulting in limitation of miniaturization of the semiconductor devices.
To solve the foregoing problems, Japanese Patent Publication No. 2007-59769, for example, proposes a technique in which through-hole electrodes of a metal or a conductive resin are formed in semiconductor chips to connect the semiconductor chips to each other.
In this technique, first, an isolation trench is formed in the substrate from the principal surface of the substrate to a desired depth, and then is filled with an insulating film, thereby forming an isolation part. Next, a MOS field effect transistor (a MOSFET) is formed in an upper portion (near the principal surface) of the substrate, and then an interlayer insulating film is formed on the substrate. Thereafter, a conductive trench is formed in a region surrounded by the isolation part to extend halfway in the substrate from the upper surface of the interlayer insulating film in the depth direction. Subsequently, the conductive trench is filled with a conductor film, thereby forming an interconnect part. Then, the back surface of the substrate is ground and polished to a degree in which the isolation part and the interconnect part are not exposed, and then wet-etched to a degree in which the isolation part and a lower portion of the interconnect part are partially exposed, thereby forming a penetration isolation part and a penetration interconnect part.
In this manner, the stacked semiconductor chips are connected to each other at a minimum distance, thereby reducing the length of interconnection, as compared to connection by wire bonding. This configuration can reduce interconnection resistance, thereby enabling high-speed operation. This configuration can also reduce a region for wire extension, and thus the size of the entire stacked-type semiconductor device is determined depending only on the size of the semiconductor chips. In addition, thickness reduction of each of the semiconductor chips to be stacked can lead to thickness reduction of the entire stacked-type semiconductor device. Accordingly, the entire stacked-type semiconductor device can be made smaller than a conventional device.